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Erik Seligman Tom Schubert M V Achutha Kiran Kuma Formal Verificatio (Paperback)
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Item specifics
- Condition
- Book Title
- Formal Verification
- Title
- Formal Verification
- Subtitle
- An Essential Toolkit for Modern VLSI Design
- EAN
- 9780323956123
- ISBN
- 9780323956123
- Release Date
- 05/26/2023
- Release Year
- 2023
- Country/Region of Manufacture
- GB
- Item Height
- 235mm
- Item Weight
- 450g
- Genre
- Computing & Internet
- Topic
- Fashion & Design
- Publication Year
- 2023
- Type
- Textbook
- Format
- Trade Paperback
- Language
- English
- Subject Area
- Computers, Technology & Engineering
- Publication Name
- Formal Verification : an Essential Toolkit for Modern Vlsi Design
- Publisher
- Elsevier Science & Technology
- Item Length
- 9.2 in
- Subject
- Programming / General, Industrial Design / Product, Microprocessors, Electronics / Microelectronics, Electronics / General, Computer Engineering
- Item Width
- 7.5 in
- Number of Pages
- 352 Pages
About this product
Product Identifiers
Publisher
Elsevier Science & Technology
ISBN-10
0323956122
ISBN-13
9780323956123
eBay Product ID (ePID)
8058367403
Product Key Features
Number of Pages
352 Pages
Language
English
Publication Name
Formal Verification : an Essential Toolkit for Modern Vlsi Design
Subject
Programming / General, Industrial Design / Product, Microprocessors, Electronics / Microelectronics, Electronics / General, Computer Engineering
Publication Year
2023
Type
Textbook
Subject Area
Computers, Technology & Engineering
Format
Trade Paperback
Dimensions
Item Length
9.2 in
Item Width
7.5 in
Additional Product Features
Edition Number
2
Intended Audience
Scholarly & Professional
Dewey Edition
23
Dewey Decimal
621.3/95
Table Of Content
Formal verification: from dreams to reality Basic formal verification algorithms Introduction to SystemVerilog Assertions Formal property verification Effective formal property verification for design exercise Effective FPV for verification Formal property verification apps for specific problems Formal equivalence verification Formal verification's greatest bloopers: the danger of false positives Dealing with complexity Formal signoff on real projects Your new FV-aware lifestyle
Synopsis
Formal Verification: An Essential Toolkit for Modern VLSI Design, Second Edition presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes. Every chapter in the second edition has been updated to reflect evolving FV practices and advanced techniques. In addition, a new chapter, Formal Signoff on Real Projects, provides guidelines for implementing signoff quality FV, completely replacing some simulation tasks with significantly more productive FV methods. After reading this book, readers will be prepared to introduce FV in their organization to effectively deploy FV techniques that increase design and validation productivity., Formal Verification: An Essential Toolkit for Modern VLSI Design Second Edition, presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes. Every chapter in the second edition has been updated to reflect evolving FV practices and advanced techniques. In addition, a new chapter, Formal Signoff on Real Projects, provides guidelines for implementing signoff quality FV, completely replacing some simulation tasks with significantly more productive FV methods. After reading this book, readers will be prepared to introduce FV in their organization to effectively deploy FV techniques that increase design and validation productivity. Key Features: Covers formal verification algorithms that help users gain full coverage without exhaustive simulation, Helps readers understand formal verification tools and how they differ from simulation tools, Shows how to create instant testbenches to gain insights into how models work and to find initial bugs, Presents insights from Intel insiders who share their hard-won knowledge and solutions to complex design problems
LC Classification Number
TK7874.75
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